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<div class="header">
  <div class="headertitle"><div class="title">FMC_Bank2_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
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<p>Flexible Memory Controller Bank2.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-pub-attribs" class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Public Attributes</h2></td></tr>
<tr class="memitem:a5bf7d23543197241fc3454bf4457f324" id="r_a5bf7d23543197241fc3454bf4457f324"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a5bf7d23543197241fc3454bf4457f324">PCR2</a></td></tr>
<tr class="memitem:a457388fbdc292927afa844272ad00782" id="r_a457388fbdc292927afa844272ad00782"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a457388fbdc292927afa844272ad00782">SR2</a></td></tr>
<tr class="memitem:aeb4961a8f61a4944138ca5bbb1475011" id="r_aeb4961a8f61a4944138ca5bbb1475011"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aeb4961a8f61a4944138ca5bbb1475011">PMEM2</a></td></tr>
<tr class="memitem:afceaece2981c4f5f2f78f32ee378bbc6" id="r_afceaece2981c4f5f2f78f32ee378bbc6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#afceaece2981c4f5f2f78f32ee378bbc6">PATT2</a></td></tr>
<tr class="memitem:aaed86fc56cbd3f7f91966bdfa5752fe8" id="r_aaed86fc56cbd3f7f91966bdfa5752fe8"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aaed86fc56cbd3f7f91966bdfa5752fe8">RESERVED0</a></td></tr>
<tr class="memitem:a4a7f2a49c73fa3a30ee72d218a9c1d1b" id="r_a4a7f2a49c73fa3a30ee72d218a9c1d1b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a4a7f2a49c73fa3a30ee72d218a9c1d1b">ECCR2</a></td></tr>
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<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Flexible Memory Controller Bank2. </p>
</div><a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
<a id="a4a7f2a49c73fa3a30ee72d218a9c1d1b" name="a4a7f2a49c73fa3a30ee72d218a9c1d1b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a4a7f2a49c73fa3a30ee72d218a9c1d1b">&#9670;&#160;</a></span>ECCR2</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FMC_Bank2_TypeDef::ECCR2</td>
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<p>NAND Flash ECC result registers 2, Address offset: 0x74 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#afceaece2981c4f5f2f78f32ee378bbc6">&#9670;&#160;</a></span>PATT2</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FMC_Bank2_TypeDef::PATT2</td>
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<p>NAND Flash Attribute memory space timing register 2, Address offset: 0x6C </p>

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<a id="a5bf7d23543197241fc3454bf4457f324" name="a5bf7d23543197241fc3454bf4457f324"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a5bf7d23543197241fc3454bf4457f324">&#9670;&#160;</a></span>PCR2</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FMC_Bank2_TypeDef::PCR2</td>
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<p>NAND Flash control register 2, Address offset: 0x60 </p>

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<a id="aeb4961a8f61a4944138ca5bbb1475011" name="aeb4961a8f61a4944138ca5bbb1475011"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aeb4961a8f61a4944138ca5bbb1475011">&#9670;&#160;</a></span>PMEM2</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FMC_Bank2_TypeDef::PMEM2</td>
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<p>NAND Flash Common memory space timing register 2, Address offset: 0x68 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aaed86fc56cbd3f7f91966bdfa5752fe8">&#9670;&#160;</a></span>RESERVED0</h2>

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          <td class="memname">uint32_t FMC_Bank2_TypeDef::RESERVED0</td>
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<p>Reserved, 0x70 </p>

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<a id="a457388fbdc292927afa844272ad00782" name="a457388fbdc292927afa844272ad00782"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a457388fbdc292927afa844272ad00782">&#9670;&#160;</a></span>SR2</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FMC_Bank2_TypeDef::SR2</td>
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<p>NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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